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High-Speed Baud-Rate Clock Recovery

Baud-rate clock recovery (CR) is gradually gaining popularity in modern serial data transmission systems since these CR techniques do not require edge-samples for extracting timing information. However, previous baud-rate techniques for high-speed serial links either rely on specific 4-bit patterns or uncorrelated random data. This work describes the modeling and design of analog filter front-end aided baud-rate CR schemes. Unlike other baud-rate schemes, this technique is not constrained by the properties of the input random data.

Firstly, the thesis develops a hardware-efficient baud-rate algorithm that requires only the slope information of the incoming random data. Called modified sign-sign minimum mean squared error (SSMMSE), this algorithm adjusts the clock sampling phase until the slope is zero through a bang-bang control loop. Secondly, the performance of a modified SSMMSE phase detector is investigated and compared with a conventional edge-sampled phase detector. It is shown that, at severe noise levels, the proposed modified SSMMSE method has better performance compared to the edge-sampled method for equal loop bandwidths.Thirdly, the thesis investigates different hardware-efficient slope detection techniques. Both passive and active filter based slope detection techniques are demonstrated in this work. In addition to slope generation, the active filter performs linear equalization as well. However, the passive filter generates the slope information at higher speeds than the active filter and also consumes less power. The two filters are used to recover a 2-GHz clock by using an external bang-bang loop.

In short, the thesis demonstrates that area and power savings can be achieved by utilizing slope information from front-end filters without compromising the performance of the CR unit.

High-Speed Baud-Rate Clock Recovery