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Boundary-Scan Tutorial

In this tutorial, you will learn the basic elements of boundary-scan architecture — where it came from, what problems it solves, and its implications on the design of an integrated- ircuit device. This tutorial also provides an overview of the data standards applicable to the boundary-scan architecture and an overview of the software tools available to perform boundary-scan-based tests.

The core reference is the 2001 version of the Standard:

    IEEE Standard 1149.1-2001 “Test Access Port and Boundary-Scan Architecture,” available from the
    IEEE, 445 Hoes Lane, PO Box 1331, Piscataway, New Jersey 08855-1331, USA.

The standard was initially created in 1990 and revised in 1993, 1994 and 2001.

For further, more recent publications on the boundary-scan architecture, see the Bibliography at the end of this tutorial.

Chapter 1: The Motivation for Boundary-Scan Architecture
Chapter 2: The Principle of Boundary-Scan Architecture
Using the Scan Path
Chapter 3: IEEE 1149.1 Device Architecture
The Instruction Register
The Instructions
Using the Instruction Register (IR)
Use of the “Capture 01” Mode
The Test Access Port (TAP)
The Bypass Register
The Identification Register
Use of the lsb = 1 Feature
Boundary-Scan Register
Providing Boundary-Scan Cells
Accessing Other Core-Logic Registers
Chapter 4: Application at the Board Level
General Strategy
Interconnect Test Example
Practical Aspects of Using Boundary-Scan Technology
Handling Non-Boundary-Scan Clusters
Access to RAM Arrays
Other Issues of Boundary Scan-to-Non-Boundary Scan Interfacing
Assembling the Final Test Program
Tester Hardware
Chapter 5: Related Data Formats
Boundary-Scan Description Language (BSDL)
What Is BSDL?
How BSDL is Used
Elements of BSDL
Hierarchical Scan Description Language (HSDL)
What Is HSDL?
HSDL Module Statements
Serial Vector Format (SVF)
What Is SVF?
SVF Structure
Standard Test And Programming Language, STAPL
What is STAPL?
Basic Structure of a STAPL program
STAPL Composers, Players and Sessions
STAPL Program Example
STAPL: final comments
Chapter 6: IEEE 1532 In-Circuit Configuration Standard
Development of the IEEE 1532 Standard
PLD Programming Environment
PLD Programming Formats and Languages
IEEE 1532 In-System Configuration Standard
Accessing Program Data and Address Registers
IEEE 1532 Instructions
Flows, Procedures and Actions
To Probe Further
Chapter 7: The IEEE 1149.6 Standard
What’s The Problem?
DC and AC-coupled Low-Voltage Differential Signals
SERializer-DESerializer, SERDES, Structures
Where Can Defects Occur?
Options for AC-Coupling Test
IEEE 1149.6 Basic Architecture
To Probe Further
Chapter 8: DFT Boundary-Scan Guidelines for Devices and Boards
Why Do We Need DFT Guidelines?
Chip-Level DFT Guidelines
Board-Level DFT Guidelines
To Probe Further
Chapter 9: Boundary-Scan Tools
Product Life Cycle Issues
Design Debug
Manufacturing Test
Field Test and Repair
Boundary-Scan Tools Requirements
Design Debug
Manufacturing Test
Field Test and Repair
Chapter 10: Recent Developments
IEEE P1687 (IJTAG) Initiative
System JTAG (SJTAG) Initiative
Boundary Scan and its Relationship with other Test Techniques
Other New Standard Developments
Chapter 11: Conclusion

Boundary-Scan Tutorial