Microprocessors today are employed for a wide range of applications, including servers, desktops, laptops, palm-pilots, automobiles, washing machines, etc. Most microprocessors used in low-end devices (home appliances) have relatively simple designs and are not very sensitive to clock speed and performance specifications. However, performance is the primary concern for most high-end microprocessors designed today. Microprocessor performance has been steadily improving because of innovations in microarchitectural design and because of shrinking process technologies.
The reduction in transistor feature sizes has increased transistor speeds and chip capacity, but has also introduced new problems in the design of modern processors. Faster transistors have enabled faster clocks, but wire delays have not improved at the same rate. Since many microprocessor structures are communication-bound rather than compute-bound, this seriously impacts the instruction-level parallelism (ILP) that these structures can help extract. Higher chip capacity and the growing number of structures on the chip also increases power consumption and design and verification complexity.
This dissertation studies the effect of recent technology trends and how they introduce trade-offs in the design of different structures on the processor. We show that by reconfiguring the hardware organization at run-time, the processor can provide many different trade-off points to the program it is executing. We examine on-line mechanisms to automatically match the hardware to the application’s needs.
Contents
Curriculum Vitae
Acknowledgments
Abstract
List of Tables
List of Figures
1 Introduction
1.1 Recent Technology Trends
1.2 Management of Trade-Offs
1.3 Thesis Statement
1.4 Dissertation Organization
2 Dynamic Adaptation Algorithms
2.1 Phase Detection
- 2.1.1 Phase Changes at Interval Boundaries
2.1.2 Positional Adaptation
2.2 Configuration Selection
- 2.2.1 Exploration
2.2.2 Prediction
2.3 Case Studies
- 2.3.1 Interval-Based Adaptation with Exploration
2.3.2 Interval-Based Adaptation with Prediction
2.3.3 Positional Adaptation with Exploration
2.3.4 Positional Adaptation with Prediction
2.4 Related Work
2.5 Summary
3 Cache Reconfiguration
3.1 Cache Design Issues
3.2 The Reconfigurable Cache Layout
- 3.2.1 Circuit Structures
3.2.2 Configurable Cache Operation
3.2.3 Configurable L2-L3 Cache
3.2.4 The Hot-and-Cold Cache
3.3 Methodology
3.4 Results
- 3.4.1 Dynamic Selection Mechanisms
3.4.2 Interval-Based Adaptation
3.4.3 TLB Reconfiguration
3.4.4 Positional Adaptation
3.4.5 Energy Consumption
3.4.6 L2/L3 Reconfiguration
3.5 Related Work
3.6 Summary
4 Trade-Offs in Clustered Microprocessors
4.1 Technology Trends
4.2 The Base Clustered Processor Architecture
- 4.2.1 The Centralized Cache
4.2.2 The Decentralized Cache
4.2.3 Interconnects
4.3 Methodology
- 4.3.1 Simulator Parameters
4.3.2 Benchmark Set
4.4 Evaluation
- 4.4.1 The Dynamically Tunable Clustered Design
4.4.2 Comparing the Dynamic Algorithms
4.4.3 Evaluating a Decentralized Cache Model
4.4.4 Sensitivity Analysis
4.5 Related Work
4.6 Summary
5 The Future Thread
5.1 Managing the In-Flight Window
5.2 The Future Thread Microarchitecture
- 5.2.1 The Base Processor
5.2.2 Overview of the Future Thread
5.2.3 Additional Hardware Structures
5.2.4 Timeout and Register Reuse
5.2.5 Redispatching an Instruction in the Primary
5.2.6 Recovery after a Branch Mispredict
5.2.7 Exploiting the IRB
5.2.8 Dynamic Partitioning of Registers
5.3 Results
- 5.3.1 Methodology
5.3.2 Analysis
5.4 Additional Hardware Requirements
5.5 Other Approaches to Improving Register File Complexity
5.6 Related Work
5.7 Summary
6 Conclusions
Bibliography
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